Memory Design Engineer

Afzal
Malik

VLSI Design Engineer specialising in memory design, analog circuit design, and mixed-signal systems — with industry experience at Zia Semiconductor and STMicroelectronics across advanced CMOS nodes.

Afzal Malik
9.3
CGPA — First Honrs
1+
yr Industry Exp
4+
VLSI Projects
1
IEEE Publication
01

About

VLSI Design Engineer with hands-on experience in memory design, analog circuit design, and mixed-signal systems. My work spans CMOS circuit design, simulation, layout, and system-level integration — with academic and industry exposure to both analog and digital VLSI flows.

Strong foundation in CMOS fundamentals, circuit analysis, and verification. I enjoy working close to silicon — building, analyzing, and validating circuits with clear performance targets.

Founder of VLSI EDGE, a technical publication for the VLSI and semiconductor engineering community. Open to opportunities in Memory Design, VLSI, and Analog/Mixed-Signal engineering.

LocationBengaluru, Karnataka, India
Current RoleDesign Engineer @ Zia Semiconductor
Also AtMemory Design Engineer @ STMicroelectronics
FounderVLSI EDGE — Technical Author & Publisher
GATE EC 2025Score 522 · Rank ~2600
02

Experience

Oct 2025 – Present
Noida, India · Hybrid
Memory Design Engineer (Subcon)
STMicroelectronics
Working on memory design projects at advanced nodes with focus on SRAM and custom memory. Involved in circuit analysis, schematic-level design, and industry characterization flows.
ESPCVCUTGENMemory DesignSRAM
Jul 2025 – Present
Bengaluru · On-site
Design Engineer
Zia Semiconductor Pvt Ltd
Full-time design engineering role focused on semiconductor circuit design and simulation at Bengaluru.
Circuit DesignSimulation
Jun 2025 – Present
India · Remote
Technical Author & Founder
VLSI EDGE
Self-employed technical author and founder of VLSI EDGE, a platform dedicated to publishing technical content for the VLSI and semiconductor engineering community.
Technical WritingVLSIPublishing
Jun 2023 – Jul 2023
Bengaluru · Hybrid
Analog Circuit Design Intern (Academic)
Under Mentorship of Dr. GS Javed, Analog Design Manager @ Intel
Designed and simulated key analog building blocks using gm/Id methodology in 180nm CMOS — including common-source & source follower amplifiers, single-stage and two-stage op-amps, and basic analog filters. Focused on meeting gain, bandwidth, stability, and power targets.
Analog Design180nm CMOSgm/IdLTSpice
View Repository ↗
03

Education

AMU
Bachelor of Technology — Electronics Engineering
Aligarh Muslim University
Nov 2021 – Jul 2025  ·  First Class with Honours  ·  CGPA: 9.338 / 10
Relevant Coursework: CMOS Circuits · Analog & Digital VLSI · Semiconductor Devices · Memory Architecture
04

Skills

Technology Nodes
7nm
28nm
180nm
TSMC 90nm (GPDK90)
EDA Tools & Environment
Cadence Virtuoso
LTSpice
Glade
Electric VLSI
ADT (Analog Designer Toolbox)
Xilinx Vivado
Eldo
GVim
Linux / Bash
GitHub
Domain Expertise
SRAM & Custom Memory Design
Memory Simulation & Characterization
CMOS Analog Circuit Design
Circuit Analysis & Simulation
Schematic-Level Design
Layout & GDSII
FPGA & RTL Design
Languages & Scripting
Verilog HDL
Python
C
Bash / Shell
05

Projects

Project 01
Phase-Locked Loop (PLL) Design — 2.4 GHz in 180nm CMOS
Aug 2024 – Jun 2025
Complete design and simulation of a 2.4 GHz PLL for wireless applications. Designed and integrated an NMOS LC VCO, TSPC-based frequency divider, PFD using NAND logic, charge pump, and loop filter. Verified locking behaviour, settling time, and stability.
180nm CMOSLTSpicePLLVCO
View on GitHub ↗
Project 02
Neural Network–based Digit Recognition — FPGA Implementation
Jan 2024 – May 2024
Handwritten digit recognition using the MNIST dataset. Implemented neural network in Verilog HDL and deployed on NEXYS A7 FPGA. Verified behaviour through simulation and on-hardware testing.
Xilinx VivadoVerilogNEXYS A7Python
View on LinkedIn ↗
Project 03
Two-Stage Op-Amp Design & Layout — 180nm CMOS
Jun 2023 – Jul 2023 · Intel Mentorship
Designed using gm/Id methodology. Targets: Gain > 60 dB, GBW ≈ 1 GHz, CL = 20 fF, Phase Margin > 50°. Full flow from schematic simulation to layout generation.
gm/IdLTSpiceADTElectric VLSI
View on GitHub ↗
Project 04
CMOS Inverter Design & Analysis — 180nm TSMC
Nov 2022
Designed CMOS inverter using TSMC 180nm models. Analysed VTC characteristics, noise margins, and switching threshold. Completed layout and verification. Extended to Cadence Virtuoso with GPDK90 — pre/post-layout simulations, parasitics extraction, and GDSII generation.
LTSpiceElectric VLSICadence VirtuosoGDSII
View on GitHub ↗
06

Publications

2024
A 5 GHz Gain-Bandwidth Operational Amplifier in 180nm CMOS Technology
4th IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI-SATA 2024) · IEEE CAS Society Bengaluru Chapter & Amrita School of Engineering · May 17, 2024
Afzal Malik et al. (5 authors)
View on IEEE Xplore ↗
07

Honours & Awards

🏆
Lead Ignite Transform Scholarship (×3)
Aligarh Education Endowment Fund
Thrice recipient of the LIT Scholarship for outstanding academic performance during the BTech program in Electronics Engineering.
🎖️
University Merit Financial Award (×3)
Aligarh Muslim University
Recipient three times for securing a position among the Top 3 students of the Electronics Engineering batch.
📊
GATE EC 2025
IIT Kanpur · Feb 2025
Score: 522 · All-India Rank ~2600 in Electronics and Communication Engineering.
🌐
IELTS Academic
British Council · Oct 2019
Overall Band Score: 7.5 — demonstrating professional working proficiency in English.
08

Contact

Open to opportunities in Memory Design, VLSI, and Analog/Mixed-Signal engineering. Feel free to reach out for collaborations, roles, or just a conversation about semiconductors.

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